Atmel AT32UC3
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Chapter 1: Start

Chapter 2: Clocks

Chapter 3: Port

Chapter 4: Interrupt

Chapter 5: Timer

Chapter 6: Real Time

Chapter 7: Serial Link


Lecture Material


Chapter 2

The little program of Chapter 1 demonstrates that the template and the STK600 setup is working. It relies on the RC-clock of 115kHZ, but for most applications that is not the clock frequency we want to use. A look in the AT32UC3A3 datasheet shows that there is a quite elaborate and adaptable logic available for even the most special clock needs, split for the different parts of the circuit. But this also means that the programming of the clocks can be quite complex.

The STK600UC3A3-template can be used with the ASF infrastructure: you can add an ASF clock module to the project and follow it's design rules. But for many application this is an overkill. Therefore a straightforward clock function is introduced that allows to program the clocks without too much headache.

Main Clock Circuit (from AT32UC3A3 datasheet).

Synchronous Clocks

The clock logic is located in the 'Power Manager (PM)'. There are three oscillators, from which a synchronous clock (for 'CPU', High Speed Bus 'HSB', Peripheral Bus A 'PBA' and Peripheral Bus B 'PBB') and 'Generic Clocks' are synthesized:

OSC0 and OSC1 are the main sources for the clocks. At startup and after a reset, both oscillators are disabled and the first part of the startup software is run by the RCSYS oscillator, until the crystal oscillators are enabled. Both on-chip oscillators of the AT32UC3A3 cannot easily be used on the STK600, since the wire length with two adapter cards needed to mount it is too long! Therefore the STK600 has a programmable and a crystal oscillator on board. You can select between the programmable oscillator, the crystal oscillator and an external oscillator via a switch. Stangely, the internal oscillator is indicated as external oscillator 'EXT' and the external oscillator is 'INT'. The output of the select-switch is connected to pin 'XTAL1".

PLL Circuit (from AT32UC3A3 datasheet).

We will use pin 18 (package QFP144) of the AT32UC3A3256 as external clock input: XTAL1-pin on the STK600 is already internally connected to pin 18 of the AT32UC3A3256. In order to use this clock input, we have to set the control words:

Synchronous Clock Divider Circuit (from AT32UC3A3 datasheet).

We will selected the output of PLL 0 as Main Clock, but before doing this, we need to specify which division factor we will apply to each one of the synchrounous clocks: CPU, HSB, PBA and PBB. We set these values in the Clock Select Register. The division factor is determined by xxxSEL as 2^(xxSEL+1):

In the Clock Mask Register clocks for individual function groups can be enabled or disabled. After reset all function groups are enabled. In order to save power, function grouops that are not used can be disabled. For now we leave all groups in the state after a reset - thus enabled.

This ends the setup of the synchronous clocks. We still have to setup the generic clocks.

Generic Clocks

Generic Clock Divider Circuit (from AT32UC3A3 datasheet).

There are 6 generic clocks. Four can be freely assigned to function groups, one is dedicated to the USB module and one to the DAC-group. Each clock can be driven either by Oscillator 0 or 1 or by the PLLs 0 or 1. For our STK600 application we will use either Oscillator 0, PLL 0 or PLL 1 - dependent on the function group. We will setup now PLL 1 so that we will have a 60MHz clock available from the output of PLL 1. This frequency can easily be further divided in the Generic Clock Modules to generate e.g. 1MHz or 10 MHz clocks

Phase-locked loop PLL 1 is connected to Oscillator 0. Again we assume that the external Oscillator 0 input frequency is 12MHz. We want a frequency of 120MHz for the PLL VCO. This clock will be divided by two at the output. It can be furthre devided later to lower frequencies for use as generic clocks for function modules. Set the PLL1 Control Register:

and enable PLL1 and wait till it is ready:

We will use the output of the PLL1 as input for the dividers of generic clocks 1..4 and will initialize them to 10MHz. Other divider ratios caneasily be implemented. The GCCTRL will be set as follows:

This setting is applied to the 4 generic clocks GCLK0 to GCLK3.
For the USB-clock (12MHz) we select: Tthe audio bitstream DAC needs a clock frequency (GCLK_ABDAC) of 12.288MHz. The 12MHz clock of Oscillator 0 is close enough. So we can use the same settings as for the USB clock.
All generic clocks are disabled.


The project Application_2 is a direct implementation of the description in the text above. Using Atmel Studio we add a directory 'support' under the 'src' directory and add two files to the 'support' directory, the file 'clock.c' and the header file 'clock.h', either by copying these files from the 'Chapter Support Files' and adding them by Atmel Studio or by creating these files with Atmel Studio and copying the contents into these files. These files use the structures and definitions in the header file 'pm240.h', which is automatically loaded via 'compiler.h'. The ASF infrastructure is not used in this allpication.

Add the following code to the program 'board_init' in 'init.c':

		// Initialize oscillators and PLL 0 for the synchronous clocks
		// Initialization for the Generic Clock via PLL 1
The description for these subprogrammes is in the text and as comments in the file 'clock.h'.

The content of the main program remains the same. Compile the program with the optimazation set to 'None' (-O0) and load the program onto the board. The LEDs should now all be on since the clock is too fast to make the individual on- and of--switching of the LEDs visible. Change in the main program the loop-count to 400000 and compile and load the program again: now the individual switching is visible, the LEDs 'run' again.

In Application_2a the different subroutines for oscillator and PLL initialization are put together in two routines, since the many subroutines don't make sense - typically they are called only once in the lifetime of a program. These routines are called 'synchronous_clock_initialization' and 'generic_clock_initialization'. In this chapter the generic clock initialization is not used and therefore only PLL 1 is initialized.

Replace the files 'clock.h' and 'clock.c' with the new ones from 'Application_2a' in 'Chapter Support' and change the content of 'board_init' in 'init.c'to:

		// Initialize oscillators and PLL 0 for the synchronous clocks
		// Initialization for the Generic Clock via PLL 1
This is much shorter and will be used in this form in the following chapters.